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Si4322
AC Characteristics (continued)
Symbol
f ref
Parameter
PLL reference frequency
Conditions/Notes
(Note 2)
Min
9
Typ
10
Max
11
Units
MHz
f res
PLL frequency resolution
20
kHz
t lock
t st1, P
t st2, P
PLL lock time
PLL startup time
PLL startup time
Frequency error < 1kHz
after 1 MHz step
Initial calibration after power-up with
running crystal oscillator
Recalibration after receiver chain
enable with running crystal oscillator
30
500
60
μ s
μ s
μ s
C xl
t POR
t sx
Crystal load capacitance,
see crystal selection guide
Internal POR pulse width
(Note 3)
Crystal oscillator startup time
Programmable in 0.5 pF steps,
tolerance +/- 10%
After V dd has reached 90% of final
value
Crystal ESR < 100 Ω
8.5
50
16
100
5
pF
ms
ms
t PBt
t wake-up
Wake-up timer clock period
Programmable wake-up time
Calibrated every 30 seconds (Note 4)
0.995
1
1
1.005
8.4*10 6
ms
ms
C in, D
Digital input capacitance
2
pF
t r, f
t r, f ,ckout
f ckout, slow
Digital output rise/fall time
Clock output rise/fall time
Slow clock frequency
15 pF pure capacitive load
10 pF pure capacitive load
Tolerance +/- 1 kHz
32
10
15
ns
ns
kHz
Not e 2:
Not e 3:
Not e 4:
Using other than a 10 MHz crystal is not recommended because the crystal referred timing and frequency parameters will
change accordingly.
During this period, commands are not accepted by the chip.
Autocalibration can be turned off.
7
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